1. Field of the Invention
This invention generally relates to physical layer (PHY) communication circuitry and, more particularly, to a system and method for using a current mode logic (CML) summing amplifier with multiple taps as feed-forward equalizer (FFE) in high speed data transmission to compensate for losses in the transmission medium.
2. Description of the Related Art
FIG. 1 is a diagram illustrating a high speed data transmission system (prior art). The data channel may be a printed circuit board (PCB) trace and include connectors and vias on the PCB board, or a length of transmission line to connect a receiver. Significant inter-symbol interference (ISI) may occur that degrades the received signal and causes errors, in the receiving data due to the dispersive behavior the channel from skin effect of metal, dielectric loss, cross-talk, and reflection due to impedance mismatches. A feed forward equalizer (FFE) and/or a decision feed-back equalizer (DFE) may be used for mitigating the problem. A feed-forward equalizer is often used in a transmitter.
FIG. 2 depicts a transversal filter FFE equalizer (prior art). The FFE consists of multiple distributed gain stages with the same number of delay taps. The delay is normally a fractional of the bit period and may be realized with either passive or active elements. In high speed data transmission, this type of FFE circuitry has the disadvantage of consuming power. It is difficult to control the delay elements, especially when more stage/taps are needed to compensate multiple post-cursor ISI. Another disadvantage is that this type of FFE cannot compensate for pre-cursor ISI.
FIG. 3 is block diagram depicting a FFE with a half-symbol spaced finite impulse response (FIR) (prior art). The input of the data stream is supplied to an 8-stage shift register, which forms the tapped delay line of the FIR filter. The shift register operates at a full-rate clock and consists of transparent latches with even and odd stages using opposite clock polarity, so each stage creates a delay of a half clock period. The eight delayed copies of the input are then multiplied by eight FIR filter coefficients and summed together as follows. First, digital signals from individual taps are supplied to exclusive-or (XOR) gates along with the respective polarity bits of the tap coefficients P0-P7. The polarity-adjusted digital signals then drive individual buffer stages with programmable tail currents. These stages generate differential output currents, each being a product of the tail current (representing the magnitude of the tap coefficient) and a polarity-adjusted delayed copy of the input data. This operation generates FIR filter partial sums. Finally, the differential currents from individual stages are summed together at a common differential resistive load, providing the final output of the FIR filter.
This FFE configuration uses latching circuitry to create half-symbol spaced delays, and even more stages are needed for more dispersive channels. XOR gates in the high speed signal path degrade the signal and add jitter to the data. Also, simple coefficient control differential circuits may not provide the right signal level and shape for optimal performance.
It would be advantageous if an FFE could operate with full rate and symbol-spaced delay, using control coefficients to shape signals with swing and slew, and provide optimal equalization performance, to compensate for pre-cursor and post-cursor inter-symbol interference in high dispersive channels.